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CY7C66013

CY7C66113

Document #: 38-08024 Rev. *B Page 56 of 61

CLOCK

CYC

Figure 25-1. Clock Timing

90%

10%

90%

10%

D−

D+

Figure 25-2. USB Data Signal Timing

OE (P2.5, input)

DATA (output)

STB

(P2.4, input)

DReadyPin (P2.3, output)

Internal Write

Internal Addr

Port0

D[23:0]

OED

OEZ

OEDR

CS (P2.6, input)

Int

(Shown for DRDY Polarity=0)

Interrupt Generated

(Ready)

Figure 25-3. HAPI Read by External Interface from USB Microcontroller

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Data Connect DSP19.2 Guida Utente Pagina 56